Logic devices such as FPGAs are used to implement large systems that include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of EDA tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, mapping, placement, routing, delay annotation, and timing analysis.
Delay annotation may involve performing logic cell delay annotation where delays related to a logic cell are computed based on the configuration and settings of the cell. Delay annotation may also involve performing routing delay annotation where delays related to a routing network (routing connections) are computed based on the structure and configuration of the routing network and the parasitic capacitive loading with respect to other routing networks in a netlist. Routing delay annotation often involves running a modeling program in order to simulate the system design. The delay values computed from delay annotation are used in timing analysis to determine whether a particular design for a system satisfies timing constraints. Because of the large number of logic cells and routing networks on a system design, delay annotation may require a significant amount of time to complete which further impacts the total compilation time of a system design.